Option for automatic insertion of blind via holes when connecting trace from opposite or inner layer to an SMD pad has been added:

Previously, assigning/changing padstacks for via holes could be done only by single selection. In 1.71 this can be done by selecting via holes in block

Arc fitting – a useful feature when designing flex boards. Trace prototypes may be routed in following fashion:

After selecting function, “Edit connection” and option “Arc miter at B Point”:

Click on selected ends of trace segments produces the following results:

Parallel routing of traces has been added specially for routing differential pairs. Depressing key combination “Shift E” prior to selecting a starting pad of a traces sets the mode for blocking several pins:

The pad that is closest to origin of the blocking rectangle is taken as starting point of the leading trace in parallel group. In above example this will be the lower pad. The leading trace may now be routed and other traces will follow parallel with specified spacing

After arriving to final destination for the leading trace, it can be connected in normal fashion, whereas, the last segment of next parallel trace may be dragged to its own final destination.

Up to eight parallel traces may be simultaneously routed using this method. When leading trace is connected, the next unconnected is taken as the leading and parallel routing continues until all in the bunch been connected or operation aborted by Esc. This principle allows for parallel routing of patterns like bellow

In some instances, it may be needed to narrow the spacing between traces to get through a tight spot. In such cases, routing of the leading trace and parallels may be terminated at any point with F4 key. With option “Allow T-connections” ON, lose ends of previously routed parallels may be grabbed in similar fashions as pads by blocking and new spacing (smaller or bigger) applied:

Several users requested option to set clearance restrictions individually for a net, net group or class of nets. This possibility has been implemented in 1.71:

Clearance violations were marked on the graphic screen by <- #violation type code, which required remembering what the code means. Now it is possible to get full violation description by hovering cursor over the marker:

“Step and repeat item” and “Rotate & Repeat” options have been added for editing copper, and board cutout outlines. Repeat options apply to copper pour/copper relief polygons too. They are also implemented in Fabrication Manager.

Optimal trace widths calculated with help of impedance calculator for every layer in the stack, may be stored as design rules. These rules will apply for all nets that have been assigned status “impedance controlled net”. This assignment means that whenever a trace for impedance controlled net is routed, the trace width will reset to width set for currently routed layer (assuming that this layer is included in the stack):

As in above example, the optimal trace width calculated for COMP.LAY was 0.020”. This width is automatically assigned to trace segment originating on this layer. After layer change to “B”, trace width switches automatically to .010”. Returning to COMP.LAYER causes automatic change of the trace segment width back to .020”:

Previously, the selection for automatic fan-out generation had to be made net wise. In 1.71, this function may be additionally restricted to selected components.

By adding possibility of importing files in DSN format (session files), EDWinXP user can now autoroute boards with help of http://www.freeroutings.net and Electra auto routers.