VHDL Editor is basically an editor for writing VHDL source files. Its working is very much similar to
any normal programming editor. All keywords present in the source are highlighted in blue. The source code
may be compiled and error messages displayed to help quick debugging.
Invoking VHDL Editor
This module may be invoked from Project Explorer in the following ways.
Right click System and select VHDL Editor from the list.
Select VHDL Editor from the Tasklist or from the Task toolbar.
Note: By default, the task toolbar will not be displayed.
It may be enabled from View menu in the Project Explorer.
Some main features of VHDL Editor are:
It compiles the source file and generates wirelist (*.wrs) output file.
The output file (*.wrs) may be imported directly to the system.
It helps to generate simulateable models in Mixed Mode & EDSpice Model Generators.
Helps to convert the (*.wrs) file to Xilinx, CUPL and JEDEC formats.
Main menu of VHDL Editor.
The VHDL Editor opens as shown:
The code can be written in the workspace and can be compiled from Build -> Compile (F7).
The circuit can be used to import EDWinXP by Build -> Compile and Import.